module edge_detect(
input sclk_1,//100M
input sclk_2,//50M
input p_in,
output p_out
);
reg p_in_reg=0;
reg dly1,dly2,dly3;
wire mux_2;
//组合逻辑产生毛刺,p_in没有和sclk_1 同步
assign mux_2 = (p_in==1'b1)? (~p_in_reg):p_in_reg;
always @(posedge sclk_1)
p_in_reg <= mux_2;
always @(posedge sclk_2)
{dly3,dly2,dly1} <= {dly2,dly1,p_in_reg};//流水移位赋值
assign p_out = dly3 ^ dly2;
endmodule
//仿真tb
`timescale 1ns/1ps
module edge_detect_tb;
reg sclk_1,sclk_2;
reg p_in;
reg p_in_r;//消除mux_2中的毛刺
wire p_out;
initial sclk_1 = 1;
//always #5 sclk_1 = ~sclk_1;
always #20 sclk_1 = ~sclk_1;
initial sclk_2 = 1;
always #10 sclk_2 = ~sclk_2;
//pin和sclk_1 进行同步
always @(posedge sclk_1)
p_in_r <= p_in;
initial begin
p_in = 0;
p_in_r = 0;
#200;
@(posedge sclk_1)
p_in = 1;
@(posedge sclk_1)
p_in = 0;
#200;
@(posedge sclk_1)
p_in = 1;
@(posedge sclk_1)
p_in = 0;
end
edge_detect edge_detect_inst(
.sclk_1(sclk_1),//100M
.sclk_2(sclk_2),//50M
.p_in(p_in_r),
.p_out(p_out)
);
endmodule
//这里使用的是run.do脚本仿真,不需要再quartus建立工程了,直接用modelsim就可以了
//run.do脚本代码
quit -sim
.main clear
vlib work
vlog edge_detect_tb.v
vlog ./../src/edge_detect.v
vsim -voptargs=+acc work.edge_detect_tb
add wave edge_detect_tb/edge_detect_inst/*
run 1us
根据图示很容易就能写出代码,
需要注意的是
组合逻辑MUX_2的变化是和p_in有关,所以输入信号p_in要同步输入时钟,消除组合逻辑中产生的毛刺
具体仿真效果可以动手做一下,不做永远不知道哪里会出错
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